(Hong Kong)
Product Summary
The H5PS5162GFR-S6C is a 512Mb(32M × 16) DDR2 SDRAM. All address and control input signals of the H5PS5162GFR-S6C are sampled on the crossing of the positive edge of CK and negative edge of CK. Output (read) data of the H5PS5162GFR-S6C is referenced to the crossings of CK and CK (both directions of crossing).
Parametrics
H5PS5162GFR-S6C absolute maximum ratings: (1)VDD, Voltage on VDD pin relative to Vss: - 1.0 V to 2.3 V; (2)VDDQ, Voltage on VDDQ pin relative to Vss: - 0.5 V to 2.3 V; (3)VDDL, Voltage on VDDL pin relative to Vss: - 0.5 V to 2.3 V; (4)VIN, VOUT, Voltage on any pin relative to Vss: - 0.5 V to 2.3 V; (5)TSTG, Storage Temperature: -55 to +100 ℃; (6)II, Input leakage current; any input 0V VIN VDD, all other balls not under test = 0V): -2 uA to 2 uA; (7)IOZ, Output leakage current, 0V VOUT VDDQ, DQ and ODT disabled: -5 uA to 5 uA.
Features
H5PS5162GFR-S6C features: (1)VDD/VDDQ= 2.0V +/- 0.1V(600/500 MHz); (2)VDD/VDDQ= 1.8V +/- 0.1V(500/400 MHz); (3)All inputs and outputs are compatible with SSTL_18 interface; (4)Fully differential clock inputs (CK, /CK) operation; (5)Double data rate interface; (6)Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS); (7)Differential Data Strobe (DQS, DQS); (8)Data outputs on DQS, DQS edges when read (edged DQ); (9)Data inputs on DQS centers when write(centered DQ); (10)On chip DLL align DQ, DQS and DQS transition with CK transition; (11)DM mask write data-in at the both rising and falling edges of the data strobe; (12)All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock; (13)Programmable CAS latency from 3 to 7 supported; (14)Programmable additive latency 0, 1, 2, 3, 4, 5 and 6 supported; (15)Programmable burst length 4/8 with both nibble sequential and interleave mode; (16)Internal four bank operations with single pulsed RAS; (17)Auto refresh and self refresh supported; (18)tRAS lockout supported; (19)8K refresh cycles /64ms; (20)JEDEC standard 84ball FBGA(x16); (21)Full strength driver option controlled by EMRS; (22)On Die Termination supported; (23)Off Chip Driver Impedance Adjustment supported; (24)Self-Refresh High Temperature Entry; (25)High Temperature Self Refresh rate supported; (26)Average Refresh Period 7.8us at lower than Tcase 85℃, 3.9us at 85℃ ＜ Tcase ＜ 95℃.
Diagrams
